1. Technical Field
This disclosure relates generally to an interconnection structure of an integrated circuit (IC) chip and, more particularly, to a structure associated with an input/output (I/O) pad having increased contact area with an electroless nickel plating layer.
2. Description of the Related Art
Flip chip bonding technology and wafer level packaging technology may employ metal bumps which are distributed over a surface of the IC chip. Such distribution of bump locations may provide several advantages of smaller package size, higher mounting density, improved electrical properties, etc. in comparison with conventional interconnection and packaging technologies.
Typically, the metal bumps are formed on respective I/O pads exposed at the chip surface. The I/O pads are chip terminals that allow signal/power access to and from chip internal circuitry. While the metal bumps may be made of mainly solder, the I/O pads may be made of aluminum or copper. Connections between the metal bump and the I/O pad may require under bump metal (UBM) layers. The UBM layers may act as an adhesive layer, a diffusion barrier, a plating base, and a solder wetting layer.
As well known in the art, the UBM layers may be composed of one or more layers and are formed through a complicated process. To form the UBM layers, several metals are deposited in sequence by sputtering, for example, which are then covered with photoresist material. The photoresist material is selectively removed by exposure and development, thus producing a desired photoresist pattern. Then bump metal is deposited using electroplating, for example, on the pre-deposited UBM metals through the photoresist pattern. After the photoresist pattern is completely removed, the UBM metals are etched using the bump metal as an etch mask. These complicated processes may incur increases in time and cost.
Electroless plating techniques, or electroplating, can uniformly and simply form a plating layer by dipping an object to be plated in a bath containing an appropriate chemical solution. Through an electrolysis process, products from the chemical solution are selectively deposited on the UBM layers on the I/O pads, thus eliminating the need for photoresist material, related processes, and etching of the UBM layers.
FIG. 1 is a sectional diagram illustrating a conventional interconnection structure of an IC chip. Referring to FIG. 1, the IC chip 10 has a tungsten pad 11 disposed on an upper portion of the chip. The tungsten pad 11 is a terminal for internal chip circuitry. An I/O pad 12 is formed of aluminum or copper on the tungsten pad 11. A top surface of the IC chip 10 is covered with a passivation layer 13 and a polymer layer 14 for protecting the chip internal circuitry. The I/O pad 12 is exposed through the passivation layer 13 and the polymer layer 14.
Minute zinc particles 15 are formed on the I/O pad 12 using a zincating, or zinc immersion, technique. The zinc particles 15 may act as a plating core during electroless plating. A surface of the I/O pad 12 is coated with a nickel layer 16 through chemical reduction. A ball-shaped solder bump 17 is formed on the nickel layer 16 acting as the UBM layer.
In this conventional interconnection structure, a contact area between the I/O pad 12 and the electroless nickel plating layer 16 is relatively small. For example, the diameter of the circular-shaped nickel layer 16 is about 135 μm. However, the diameter or width of the I/O pad 12 is about 70 μm, and further, an exposed part of the I/O pad 12 is only about 50 μm in diameter. This may cause a difference between the size of the I/O pad 12 allowed at the chip level and the size of the plating layer 16 required at the package level.
Since the contact area between the I/O pad 12 and the plating layer 16 is limited to the exposed part of the I/O pad 12, metallic joints between both metal layers 12 and 16 may often be unsatisfactory. Therefore, when the metallic joints are subjected to thermally inducted stress, cracks or delaminations may occur in the metallic joints, which raises concerns regarding yield and reliability.
Embodiments of the invention address these and other disadvantages of the conventional art.